This invention relates generally to memory in integrated circuit devices. More particularly, this invention relates to a DDR memory implementation on an integrated circuit.
Due to rapid progress in design techniques and process technology, the speed of integrated circuit (IC) devices has increased considerably. Such a rapid change in the speed of IC devices has also led to increasingly demanding requirements on the memory devices that interface with these IC's. Besides having a high storage capacity, modern memory chips must be able to interface with other chips at increasingly faster speeds. Consequently, the use of Double Data Rate (DDR) memory devices for faster speed has become increasingly common. DDR memory devices differ from conventional memory devices by enabling data transfer on both the rising and falling edge of the clock, thereby doubling the peak throughput of the memory device.
A DDR memory device transmits both data (DQ) and its associated clock strobe (DQS). FIG. 1 shows the timing relationship of the DQ and the DQS signals for DDR applications. The DQ is transmitted from the DDR memory chip, edge-aligned with the DQS strobe. Both DQ and DQS are clocked off the system clock. The receiving IC device, e.g. an FPGA device, receives the edge-aligned DQ and DQS, and phase-shifts the DQS by 90° in order to align the DQS strobe to the center of the data eye. This 90° phase-shift is achieved by adding a delay chain in the DQS path with a delay equal to ¼ the system clock frequency (See FIG. 2).
FIG. 2 shows an exemplary circuit for controlling the DQS delay. Input pins 210 and 220 receive the DQ and DQS signals, respectively. Delay chain 230 provides a delayed DQS signal to DDR capture registers 250. Delay chain 230 is controlled by a control signal 260 provided by DLL 240. DLL 240 continuously tracks the system clock frequency and provides a control signal 260 that maintains the desired delay in the DQS signal.
During operation, the system clock can drift in time due to changing operating conditions such as a change in temperature or voltage. To compensate for this drift, the memory device uses a clock-drift tracking delay chain 230 with variable delay that will track the system clock in order to always provide a ¼ clock period delay.
The delay chain 230 is controlled by a 6-bit binary-encoded control signal 260 generated from DLL 240. Because the 6-bit control signal 260 is continuously changing to track the drifting system clock, the 6-bit control signal can change during the time DQS is propagating through the delay chain 230. This change can lead to an incorrect delay for the 90° DQS phase offset.
Additionally, the 6-bit control signal must propagate from DLL 240 to delay chain 230 and therefore the 6 control signals may arrive at delay chain 230 at different times, thereby causing the delay chain to be momentarily set to an incorrect delay. An arriving DQS strobe at this time would not be correctly aligned to the center of the data eye.
Further, the binary-encoded 6-bit control can lead to widely varying delays. For example, if the control signal from the DLL is going from 011111 to 100000, the delay chain could be momentarily set to or 000000 or somewhere in between.
FIG. 3 illustrates a case where control signal 260 is momentarily set to a lower value when DQS is passing through it. The delay cell will add some additional delay to DQS while control signal 260 is in this incorrect state. The resulting DQS signal will be phase shifted past the center of the data eye.
FIG. 4 illustrates a case where control signal 260 is momentarily set to a higher value when DQS is passing through it. The delay cell will be set to a smaller delay while control signal 260 is in this incorrect state. The resulting DQS signal will be phase shifted before the center of the data eye.
An additional problem with providing an accurate delay signal to delay chain 230 arises in the DLL 240. DLL 240 includes a plurality of delay chains that are used to accurately control the delay of the input signal to the DLL. FIG. 5 illustrates how a glitch can occur when there is more than one signal path, 410 and 420 in the delay chain. As can be seen in FIG. 5, a glitch may appear at the output 440 if the multiplexer 430 switches from signal path 420 to signal path 410 while the input signal is passing through the delay chain.
Additionally, as shown in FIG. 6, jitter may occur when two delay elements in a delay chain are switched in opposite directions at the same time, i.e. one is switched on while the other is switched off. For example, the inverter S0 has a delay of 200 ps and inverter S1 has a delay of 300 ps. If a 350 ps delay is needed instead of a 250 ps delay then S0 must be turned off and S1 must be turned on. When the delay time is switched from 250 ps to 350 ps, the delay signal passing through the delay chain should be between 250–350 ps. Instead, during switching one output edge gets a 500 ps delay, thereby producing jitter on the output.
In view of the above, there is a need in the art for a delay chain that does not cause jitter and glitch at the delay chain output signal. Additionally, there is a need in the art for providing a control signal for accurately controlling the delay of a delay chain in a DDR implementation.